Organic EL (electroluminescent) displays are conventionally known as being thin display devices featuring high image quality and low power consumption. The organic EL display has a plurality of pixel circuits arranged in a matrix, each circuit including an organic EL element, which is a light-emitting display element driven by a current, and a drive transistor for driving the element.
The method for controlling the amount of current to be applied to current-driven display elements such as organic EL elements as above are generally classified into: a constant-current control mode (or a current-programmed drive mode) in which the current that is to be applied to display elements is controlled by data signal currents flowing through data signal line electrodes of the display elements; and a constant-voltage control mode (or a voltage-programmed drive mode) in which the current that is to be applied to display elements is controlled by voltages corresponding to data signal voltages. Among these modes, when the constant-voltage control mode is used for display on an organic EL display, it is necessary to compensate for current reduction (luminance decay) due to variations in the threshold voltage among drive transistors and increased resistance caused by deterioration of organic EL elements over time. On the other hand, in the case of the constant-current control mode, the values for data signal currents are controlled such that constant currents are applied to organic EL elements regardless of the threshold voltages and internal resistance of the organic EL elements, and therefore, the compensation as mentioned above is normally unnecessary. However, the constant-current control mode is known to require more drive transistors and more wiring lines than the constant-voltage control mode, which leads to a lower aperture ratio, and therefore, the constant-voltage control mode is widely employed.
Here, various configurations of pixel circuits that are employed with the constant-voltage control mode and perform compensation operations as above are conventionally known. Japanese Laid-Open Patent Publication No. 2005-31630 describes a pixel circuit 91 shown in FIG. 20.
FIG. 20 is a circuit diagram of the pixel circuit 91. The pixel circuit 91 includes six TFTs (thin-film transistors) 11 to 16, an organic EL element 17, and a capacitor 18, as shown in FIG. 20. All of the six TFTs 11 to 16 are p-channel transistors. Moreover, the pixel circuit 91 is connected to two scanning signal lines Gi and G(i-1), a control line Ei, a data line Sj, a pair of power lines VPj, and an electrode having a common potential Vcom. The TFT 11 has a source terminal connected to one conductive terminal of the TFT 13 and one conductive terminal of the TFT 15, and the TFT 11 also has a drain terminal connected to one conductive terminal of the TFT 12 and one conductive terminal of the TFT 14. The other conductive terminal of the TFT 13 is connected to one of the power lines VPj, which provides a power supply potential VDD. The other conductive terminal of the TFT 15 is connected to the data line Sj. The other conductive terminal of the TFT 14 is connected to an anode terminal of the organic EL element 17. The aforementioned conductive terminal of the TFT 12 is connected to a gate terminal of the TFT 11, and the other conductive terminal of the TFT 12 is connected to the drain terminal of the TFT 11. The TFT 16 is connected at one conductive terminal to the other power line VPj, which provides an initialization potential Vini, and at the other conductive terminal to a control terminal of the TFT 11. The data holding capacitor 18 is connected at one terminal to the control terminal of the TFT 11 as well and at the other terminal to the power line VP that provides the power supply potential VDD. The organic EL element 17 has the common potential Vcom applied at its cathode terminal. The scanning signal line Gi is connected to a gate terminal of each of the TFTs 12 and 15. The scanning signal line G(i-1) is connected to a gate terminal of the TFT 16. The control line Ei is connected to a gate terminal of each of the TFTs 13 and 14.
Furthermore, US Patent Application Publication No. 2006/103322 describes a pixel circuit 92 shown in FIG. 21. FIG. 21 is a circuit diagram of the pixel circuit 92. The pixel circuit 92 includes six TFTs 21 to 26, an organic EL element 17, and a data holding capacitor 28, as shown in FIG. 21. All of the six TFTs 21 to 26 are p-channel transistors. Moreover, the pixel circuit 92 is connected to a scanning signal line Gi, a control line Ei, an initialization control line Ii, a data line Sj, a pair of power lines VPj, and an electrode having a common potential Vcom. The TFT 22 has a source terminal connected to one of the power lines VPi, which provides a power supply potential VDD, and the TFT 22 also has a drain terminal connected to one conductive terminal of the TFT 23. The other conductive terminal of the TFT 23 is connected to a gate terminal of the TFT 22. Moreover, the TFT 25 is connected at one conductive terminal to a drain terminal of the TFT 22 and at the other conductive terminal to an anode terminal of the organic EL element 17. Furthermore, the TFT 21 is connected at one conductive terminal to the data line Sj and at the other conductive terminal to one terminal of the data holding capacitor 28. The TFTs 24 and 26 are connected at one conductive terminal to the other power line VPj, which provides an initialization potential Vini. The TFT 24 is connected at the other conductive terminal to the other terminal of the data holding capacitor 28, and the other conductive terminal of the TFT 26 is connected to the opposite terminal of the data holding capacitor 28. The other terminal of the data holding capacitor 28 is connected to the gate terminal of the TFT 22. The organic EL element 17 has the common potential Vcom applied at its cathode terminal. The scanning signal line Gi is connected to a gate terminal of each of the TFTs 21 and 23. The initialization control line Ii is connected to a gate terminal of the TFT 24. The control line Ei is connected to a gate terminal of each of the TFTs 25 and 26.
Furthermore, Japanese Laid-Open Patent Publication No. 2003-202833 describes a pixel circuit 93 shown in FIG. 22. FIG. 22 is a circuit diagram of the pixel circuit 93. The pixel circuit 93 includes six TFTs 31 to 36, an organic EL element 17, and a data holding capacitor 38, as shown in FIG. 22. All of the six TFTs 31 to 36 are n-channel transistors. The pixel circuit 93 is connected to a scanning signal line Gi, control lines Eai to Edi, a data line Sj, a power line VPj, and an electrode having a common potential Vcom. The TFT 31, which is a drive transistor, has a drain terminal connected to the power line VPj, which provides a power supply potential VDD, via the TFT 35 on a current path. Moreover, the TFT 31 has a source terminal connected to an anode terminal of the organic EL element 17 via the TFT 32 on a current path. The TFT 36 is connected at one conductive terminal to the drain terminal of the TFT 31 and at the other conductive terminal to a gate terminal of the TFT 31. Moreover, the TFT 34 is connected at one conductive terminal to the data line Sj and at the other conductive terminal to the source terminal of the TFT 31. Furthermore, the data holding capacitor 38 is connected at one terminal to the electrode having the common potential Vcom via the TFT 33. The terminal of the data holding capacitor 38 is also connected to the source terminal of the TFT 31 via the TFT 32. The organic EL element 17 has the common potential Vcom applied at its cathode terminal. The scanning signal line Gi is connected to a gate terminal of the TFT 34. Moreover, the control line Edi is connected to a gate terminal of the TFT 33. Furthermore, the control line Eai is connected to a gate terminal of the TFT 36. The control line Eci is connected to a gate terminal of the TFT 32. Moreover, the control line Ebi is connected to a gate terminal of the TFT 35.
Furthermore, Japanese Laid-Open Patent Publication No. 2011-34039 describes a pixel circuit 94 shown in FIG. 23. FIG. 23 is a circuit diagram of the pixel circuit 94. The pixel circuit 94 includes three TFTs 41 to 43, an organic EL element 17, two data holding capacitors 48a and 48b, and a threshold holding capacitor 49, as shown in FIG. 23. All of the three TFTs 41 to 43 are p-channel transistors. The pixel circuit 94 is connected to a scanning signal line Gi, a control line Ei, a data line Sj, a power line VPi, and an electrode having a common potential Vcom. The TFT 41 is connected at one conductive terminal to the data line Sj and at the other conductive terminal to one terminal of each of the two data holding capacitors 48a and 48b. Of the two data holding capacitors 48a and 48b, the data holding capacitor 48a is connected at the other terminal to a gate terminal of the TFT 42, and the data holding capacitor 48b is connected at the other terminal to the power line VPi. The TFT 42 has a drain terminal connected to the power line VPi and a source terminal connected to an anode terminal of the organic EL element 17. The organic EL element 17 has the common potential Vcom applied at its cathode terminal. The TFT 43 is connected at one conductive terminal to a gate terminal of the TFT 42 and at the other conductive terminal to a source terminal of the TFT 42. The scanning signal line Gi is connected to a gate terminal of the TFT 41. The control line Ei is connected to a gate terminal of the TFT 43.
Note that Japanese Laid-Open Patent Publication No. 2007-79580 describes a pixel circuit 95 shown in FIG. 24, which is similar to the pixel circuit 92 shown in FIG. 21. FIG. 24 is a circuit diagram of the pixel circuit 95. The pixel circuit 95 includes six TFTs 11 to 16, an organic EL element 17, and a capacitor 18, which are the same components as in the pixel circuit 92, and the pixel circuit 95 further includes an auxiliary capacitor Caux, as shown in FIG. 24. However, the TFT 12 is connected at the conductive terminal to the source terminal, rather than the drain terminal, of the TFT 11. Moreover, the TFT 15 is connected at the conductive terminal to the drain terminal, rather than the source terminal, of the TFT 11. In addition, as with the capacitor 18, the auxiliary capacitor Caux is connected at one terminal to the control terminal of the TFT 11 and at the other end to the scanning signal line Gi, the potential of which is variable.